The present invention relates to memory devices, and more particularly to memories having a burst mode access.
FIG. 1 shows a memory 110 having an array of 1-bit memory locations (or "cells") M-0 through M-15. Each location M-i has unique address i. Consecutive memory locations M-0 through M-7 are arranged consecutively in the first row of the array, and are connected to word line WL-0. Consecutive locations M-8 through M-15 are arranged consecutively in the second row and are connected to word line WL-1. The memory cells of each column are connected to one of the eight bit lines BL-0 through BL-7.
In order to read location M-i, the address i is provided to address inputs 112 connected to X-decoder (row decoder) 114 and Y-decoder (column decoder) 116. X-decoder 114 decodes the address and activates the corresponding word line WL-0 or WL-1. All the memory cells connected to the activated word line provide their states on the corresponding bit lines BL-0 through BL-7. Y-decoder 116 decodes the address i and signals Y-select circuit 118 to select the column (that is, the bit line) connected to the memory location M-i. Y-select circuit 118 connects the selected bit line to sense amplifier circuit 120 which suitably amplifies the bit line signal. The amplified signal is latched into register 130 from which the signal is read to output buffer 134. Output buffer 134 converts the signal to specified levels as required by external memory reading devices (which are not shown), and provides the signal to the external devices on output DOUT.
When a memory is read sequentially (that is, consecutive reads access memory locations at consecutive addresses), the memory access can be made faster by reading from the array several consecutive locations simultaneously. Such a "burst mode" access is provided by memory 202 of FIG. 2. In memory 202, Y-select circuit 210 selects four consecutive bit lines BL-0 through BL-3 or BL-4 through BL-7 to latch contents of four consecutive locations simultaneously into register circuit 220. Register circuit 220 contains four registers 220.0 through 220.3, one for each selected bit line. Registers 220.0 through 220.3 are read one by one, through register select circuit 224, by output buffer 134. Since only one address decoding operation and only one memory array access are performed to read four consecutive memory locations, the memory reads are speeded up.
It is desirable to provide a still faster sequential reading so as to enable the memory to keep up with high speed processors and other high speed memory reading devices.